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1 ltc1645 dual-channel hot swap controller/power sequencer the ltc ? 1645 is a 2-channel hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. using external n-channel pass transistors, the supply voltages can be ramped at a programmable rate. two high side switch drivers control the n-channel gates for supply voltages ranging from 1.2v to 12v. the two channels can be set to ramp up and down separately, or they can be programmed to rise and fall simultaneously, ensuring power supply tracking at the two outputs. programmable electronic circuit breakers protect against shorts at either output. the reset output can be used to generate a system reset when a supply voltage falls below a user-programmed voltage. an additional spare com- parator is available for monitoring a second supply voltage. the ltc1645 is available in the 8- and 14-pin so packages. n hot board insertion n power supply sequencing n electronic circuit breaker n allows safe board insertion and removal from a live backplane n programmable power supply sequencing n programmable electronic circuit breaker n user-programmable supply voltage power-up and power-down rate n high side drivers for external n-channel fets n controls supply voltages from 1.2v to 12v n ensures proper power-up behavior n undervoltage lockout n glitch filter protects against spurious reset signals , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. 5v and 3.3v hot swap 5v and 3.3v hot swap waveforms on 5v/div gate n 10v/div v out2 5v/div v out1 5v/div 0.005 * irf7413 irf7413 0.005 * 10 10 10k c load2 c load1 v out1 5v 5a v out2 3.3v 5a 6 2 3 4 7 8 5 1 1645 ta01 0.01 f 25v 0.01 f 25v on v in2 v in1 on gnd gnd plug-in card backplane sense1 v cc2 gate1 sense2 gate2 ltc1645 (8-lead) + + connector 1 connector 2 v cc1 *lrf1206-01-r005-j (irc) features descriptio u applicatio s u typical applicatio u
2 ltc1645 supply voltage (v cc1 , v cc2 ) ................................. 13.2v input voltage fb, on, comp + ..................... C 0.3v to (v cc1 + 0.3v) timer ................................................. C 0.3v to 2.5v sense1 ..................... (v cc1 C 0.7v) to (v cc1 + 0.3v) sense2 ...................... (v cc1 C 0.7v) to (v cc2 + 0.3v) output voltage reset, compout, fault .....................C 0.3v to 16v gate1, gate2 ................. internally limited (note 3) output current gate1, gate2 ............................................... 20ma operating temperature range ltc1645c ............................................... 0 c to 70 c ltc1645i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c symbol parameter conditions min typ max units dc characteristics i cc1 v cc1 supply current on = v cc1 = 5v, v cc2 = 3.3v l 1.1 2.0 ma i cc2 v cc2 supply current on = v cc1 = 5v, v cc2 = 3.3v l 0.28 0.4 ma v lko1 v cc1 undervoltage lockout high to low l 2.16 2.23 2.3 v v lko2 v cc2 undervoltage lockout high to low l 1.06 1.12 1.18 v v lkh n v cc n undervoltage lockout hysteresis 25 mv v fb fb pin voltage threshold high to low l 1.226 1.238 1.250 v d v fb fb pin threshold line regulation high to low, v cc1 = 2.375v to 12v l 14 mv v fbhst fb pin voltage threshold hysteresis 5 mv v comp comp + pin voltage threshold high to low l 1.226 1.238 1.250 v d v comp comp + pin threshold line regulation high to low, v cc1 = 2.375v to 12v l 14 mv v comphst comp + pin voltage threshold hysteresis 5 mv (note 1) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.375v v cc1 12v, 1.2v v cc2 12v unless otherwise noted (note 2). top view s package 14-lead plastic so 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc2 sense2 gate2 fault reset fb gnd v cc1 sense1 gate1 timer on compout comp + t jmax = 125 c, q ja = 110 c/ w top view v cc1 sense1 gate1 on v cc2 sense2 gate2 gnd s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 t jmax = 125 c, q ja = 150 c/ w order part number s8 part marking 1645 1645i LTC1645CS8 ltc1645is8 order part number LTC1645CS ltc1645is consult factory for military grade parts. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 ltc1645 symbol parameter conditions min typ max units v tm timer pin voltage threshold l 1.212 1.230 1.248 v d v tm timer pin threshold line regulation v cc1 = 2.375v to 12v l 19 mv i tm timer pin current timer on, v timer = 0.6v, v cc1 = 5v l C 2.3 C 2 C 1.7 m a timer off, v timer = 1.5v 12 ma v cb1 circuit breaker trip voltage 1 v cb1 = (v cc1 C v sense1 ) l 46 50 56 mv v cb2 circuit breaker trip voltage 2 v cb2 = (v cc2 C v sense2 ) l 46 50 56 mv t cbd n circuit breaker trip delay v cb n = (v cc n C v sense n ) > 60mv 1.5 m s i cp gate n pin output current on = 2.2v, v gate n = v cc n , v cc1 = 5v, v cc2 = 3.3v l C 12.5 C 10 C 7.5 m a on = 0.7v, v gate n = v cc n , v cc1 = 5v, v cc2 = 3.3v l 30 40 50 m a on = 0.3v, v gate n = v cc n , v cc1 = 5v, v cc2 = 3.3v 12 ma d v gate n external n-channel gate drive d v gate n = (v gate n C v cc n ) l 4.5 16 v v onfpd on pin fast pull-down threshold low to high l 0.375 0.4 0.425 v high to low, fast pull-down engaged l 0.35 0.375 0.4 v v on1 on pin threshold #1 low to high, gate1 turns on l 0.8 0.825 0.85 v high to low, gate1 turns off l 0.775 0.8 0.825 v v on2 on pin threshold #2 low to high, gate2 turns on l 2 2.025 2.050 v high to low, gate2 turns off l 1.975 2 2.025 v v onhyst on pin hysteresis 25 mv i on on pin input current v cc1 = 5v, v cc2 = 3.3v l 0.01 2 m a v ol output low voltage reset, fault, compout, i out = 1.6ma, v cc1 = 5v l 0.16 0.4 v note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.375v v cc1 12v, 1.2v v cc2 12v unless otherwise noted (note 2). note 3: an internal zener on the gate n pins clamps the charge pump voltage to a typical maximum operating voltage of 22v. external overdrive of a gate pin (for example, from capacitive coupling of v cc n glitches) beyond the internal zener voltage may damage the device. if a lower gate n pin clamp voltage is desired, use an external zener diode. v cc1 supply current vs voltage v cc2 supply current vs voltage v cc1 (v) 0 i cc1 (ma) 1.0 2.0 3.0 0.5 1.5 2.5 46810 1645 g01 12 3 257911 t a = 25 c v cc2 = 1.5v v cc2 = 12v v cc2 (v) 0 i cc2 (ma) 0.5 1.5 2.0 2.5 3.5 1 5 7 1645 g02 1.0 3.0 4 9 10 11 12 2 3 68 t a = 25 c v cc1 = 2.375v v cc1 = 12v supply current vs temperature temperature ( c) ?0 0.8 1.0 1.4 20 60 1645 g03 0.6 0.4 ?0 0 40 80 100 0.2 0 1.2 i cc n (ma) v cc1 = 5v v cc2 = 3.3v i cc1 i cc2 electrical characteristics typical perfor a ce characteristics uw
4 ltc1645 gate voltage vs supply voltage gate voltage vs temperature glitch filter time vs feedback transient reset, fault, compout output voltage vs temperature reset, fault, compout output voltage vs v cc1 fast pull-down current vs v cc1 highest v cc (v) 2 gate n (v) 15 20 25 10 1645 g04 10 5 0 4 6 8 311 5 7 9 12 t a = 25 c temperature ( c) ?0 14.0 gate n (v) 14.2 14.6 14.8 15.0 16.0 15.4 0 40 60 1645 g05 14.4 15.6 15.8 15.2 ?0 20 80 100 v cc1 = 5v v cc2 = 3.3v feedback transient (mv) 0 0 glitch filter time ( s) 10 30 40 50 100 70 80 160 200 1645 g06 20 80 90 60 40 120 240 280 t a = 25 c temperature ( c) ?0 0 output voltage (mv) 50 150 200 250 40 60 80 450 1645 g07 100 20 0 20 100 300 350 400 v cc1 = 5v sink current = 3ma sink current = 1.6ma v cc1 (v) 2 output voltage (mv) 800 700 600 500 400 300 200 100 0 10 1645 g08 468 12 9 357 11 t a = 25 c sink current = 3ma sink current = 1.6ma v cc1 (v) 23 5 9 11 fast pull-down current (ma) 14 16 18 10 1645 g09 12 10 13 15 17 11 9 8 4 6 8 7 12 t a = 25 c v cc2 = 1.5v typical perfor a ce characteristics uw
5 ltc1645 v cc2 (pin 1/pin 1): positive supply input. v cc2 can range from 1.2v to 12v for normal operation. i cc2 is typically 0.2ma. an undervoltage lockout circuit disables the ltc1645 whenever the voltage at v cc2 is less than 1.12v. sense2 (pin 2/pin 2): v cc2 circuit breaker set pin. with a sense resistor placed in the supply path between v cc2 and sense2, the circuit breaker trips when the voltage across the resistor exceeds 50mv for more than 1.5 m s. if the circuit breaker trip current is set to twice the normal operating current, only 25mv is dropped across the sense resistor during normal operation. to disable the circuit breaker, short v cc2 and sense2 together. gate2 (pin 3/pin 3): channel 2 high side gate drive. connect to the gate of an external n-channel mosfet. an internal charge pump guarantees at least 4.5v of gate drive. the charge pump is powered by the higher of v cc1 and v cc2 . when the on pin exceeds 2v, gate2 is turned on by connecting a 10 m a current source from the charge pump output to the gate2 pin and the voltage starts to ramp up with a slope dv/dt = 10 m a/c gate2 . while the on pin is below 2v but above 0.4v, a 40 m a current source pulls gate2 toward ground. if the on pin is below 0.4v, the circuit breaker trips or the undervoltage lockout circuit trips, the gate2 pin is immediately pulled to ground with a 12ma (typ) current source. fault (pin 4/na): circuit breaker fault. fault is an open-drain output that pulls low when the circuit breaker function trips. the circuit breaker is reset by pulling the on pin below 0.4v. an external pull-up is required to generate a logic high at the fault pin. when the on pin is low, fault will release. the circuit breaker can be programmed to automatically reset by connecting the fault pin to the on pin. in this circuit configuration, if a logic device is driving the on pin, use a series resistor between the logic output and the on pin to prevent large currents from flowing. reset (pin 5/na): open-drain reset output. the reset pin is pulled low when the voltage at the fb pin goes below 1.238v or v cc1 is below the undervoltage lockout thresh- old. the reset pin goes high one timing cycle after the voltage at the fb pin goes above the fb pin threshold. the on pin must remain above 0.8v during this timing cycle. an external pull-up is required to generate a logic high at the reset pin. fb (pin 6/na): reset comparator input. the fb pin is used to monitor the output supply voltage with an external resistive divider. when the voltage on the fb pin is lower than 1.238v, the reset pin is pulled low. a glitch filter on the fb pin prevents fast transients from forcing reset low. when the voltage on the fb pin rises above the trip point, the reset pin goes high after one timing cycle. gnd (pin 7/pin 4): ground. connect to a ground plane for optimum performance. comp + (pin 8/na): spare comparator noninverting in- put. when the voltage on comp + is lower than 1.238v, compout pulls low. compout (pin 9/na): open-drain spare comparator output. compout pulls low when the voltage on comp + is below 1.238v or v cc1 is below the undervoltage lockout threshold. an external pull-up is required to generate a logic high at the compout pin. on (pin 10/pin 5): analog control input. if the on pin voltage is below 0.4v, both gate1 and gate2 are imme- diately pulled to ground. while the voltage is between 0.4v and 0.8v, both gate1 and gate2 are each pulled to ground with a 40 m a current source. while the voltage is between 0.8v and 2v, the gate1 pull-up is turned on after one timing cycle, but gate2 continues to be pulled to ground with a 40 m a current source. when the voltage exceeds 2v, both the gate1 and gate2 pull-ups are turned on one timing cycle after the voltage exceeds 0.8v. the on pin is also used to reset the electronic circuit breaker. if the on pin is brought below and then above 0.4v following the trip of the circuit breaker, the circuit breaker resets, and a normal power-up sequence occurs. timer: (pin 11/na): system timing pin. the timer pin requires an external capacitor to ground to generate a timing delay. the pin is used to set the delay before the reset pin goes high after the output supply voltage is good as sensed by the fb pin. it is also used to set the delay between the on pin exceeding 0.8v and the gate1 and gate2 pins turning on (gate2 turns on only if the on pin exceeds 2v). (14-lead package/8-lead package) uu u pi fu ctio s
6 ltc1645 (14-lead package/8-lead package) whenever the timer is inactive, an internal n-channel fet shorts the timer pin to ground. activating the timer connects a 2 m a current source from v cc1 to the timer pin and the voltage starts to ramp up with a slope dv/dt = 2 m a/ c timer . when the voltage reaches the trip point (1.23v), the timer is reset by pulling the timer pin back to ground. the timer period is (1.23v ? c timer )/2 m a. gate1 (pin 12/pin 6): channel 1 high side gate drive. connect to the gate of an external n-channel mosfet. an internal charge pump guarantees at least 4.5v of gate drive. the charge pump is powered by the higher of v cc1 and v cc2 . when the on pin exceeds 0.8v, gate1 is turned on by connecting a 10 m a current source from the charge pump output to the gate1 pin and the voltage starts to ramp up with a slope dv/dt = 10 m a/c gate1 . while the on pin is below 0.8v but above 0.4v, a 40 m a current source pulls gate1 toward ground. if the on pin is below 0.4v, the circuit breaker trips or the undervoltage lockout circuit trips, the gate1 pin is immediately pulled to ground with a 12ma (typ) current source. sense1 (pin 13/pin 7): v cc1 circuit breaker set pin. with a sense resistor placed in the supply path between v cc1 and sense1, the circuit breaker trips when the voltage across the resistor exceeds 50mv for more than 1.5 m s. if the circuit breaker trip current is set to twice the normal operating current, only 25mv is dropped across the sense resistor during normal operation. to disable the circuit breaker, short v cc1 and sense1 together. v cc1 (pin 14/pin 8): positive supply input. v cc1 can range from 2.375v to 12v for normal operation. i cc1 is typically 1ma. an undervoltage lockout circuit disables the chip whenever the voltage at v cc1 is less than 2.23v. all internal logic is powered by v cc1 . + + + + + + + + 2.23v uvl 2v on 0.8v 0.4v ref 1.5 s filter 1.12v uvl 1.5 s filter logic glitch filter ref ref 4 charge pump 1.238v reference 50mv 50mv 2 a + + 10 v cc1 14 sense1 13 v cc2 1 sense2 2 gate1 12 gate2 3 fb 6 reset 5 gnd 7 comp + 8 compout 9 fault 4 1645 bd timer 11 uu u pi fu ctio s block diagra w
7 ltc1645 hot circuit insertion when a circuit board is inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge. these transient currents can cause permanent damage to the connector pins and produce glitches on the system supply, resetting other boards in the system. the ltc1645 is designed to turn a boards supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the chip provides a system reset signal and a spare comparator to indicate when board supply voltages drop below user- programmable voltages, and a fault signal to indicate if an overcurrent condition has occurred. the ltc1645 can be located before or after the connector as shown in figure 1. a staggered pcb connector can sequence pin connections when plugging and unplugging circuit boards. alternatively, the control signal can be generated by processor control. power supply tracking and sequencing some applications require that the potential difference between two power supplies not exceed a certain voltage. this requirement applies during power-up and power- down as well as during steady state operation, often to prevent latch-up in a dual supply asic. other systems require one supply to come up after another, for example, if a system clock needs to start before a block of logic. typical dual supplies or backplane connections may come up at arbitrary rates depending on load current, capacitor size, soft-start rates, etc. traditional solutions are cum- bersome and require complex circuitry to meet the power supply requirements. the ltc1645 provides a simple solution to power supply tracking and sequencing needs. the ltc1645 guarantees supply tracking by ramping the supplies up and down together (see figure 15). the sequencing capabilities of the ltc1645 allow nearly any combination of supply ramping (e.g., see figure 17) to satisfy various sequenc- ing specifications. see the power supply tracking and sequencing applications section for more information. applicatio s i for atio wu uu sense fault v cc v out fault on on gnd gate ltc1645 backplane connector staggered pcb edge connector c load + v cc (a) hot swap controller on motherboard sense fault v cc v out fault on gnd gate ltc1645 1645 f01 c load + v cc backplane connector staggered pcb edge connector (b) hot swap controller on daughterboard figure 1. staggered pins connection
8 ltc1645 power supply ramping the power supplies on a board are controlled by placing external n-channel pass transistors in the power paths as shown in figure 2. consult table 1 for a selection of n-channel fets suitable for use with the ltc1645. r sense1 and r sense2 provide current fault detection and r1 and r2 prevent high frequency oscillation. by ramping the gates of the pass transistors up and down at a controlled rate, the transient surge current (i = c ? dv/dt) drawn from the main backplane supply is limited to a safe value when the board makes connection. when power is first applied to the chip, the gates of the n-channels (gate1 and gate2 pins) are pulled low. after the on pin is held above 0.8v for at least one timing cycle, the voltage at gate1 begins to rise with a slope equal to dv/dt = 10 m a/c1 (figure 3), where c1 is the external capacitor connected between the gate1 pin and gnd. if the on pin is brought above 2v (and the on pin has been held above 0.8v for at least one timing cycle), the voltage at gate2 begins to rise with a slope equal to dv/dt = 10 m a/c2. the ramp time for each supply is t = (v cc n ? c n )/10 m a. if the on pin is pulled below 2v for gate2 or 0.8v for gate1 (but above 0.4v), a 40 m a current source is connected from gate n to gnd, and the voltage at the gate n pin will ramp down, as shown in figure 4. ringing good engineering practice calls for bypassing the supply rail of any circuit. bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. if power is connected abruptly, the bypass capacitors slow the rate of rise of voltage and heavily damp any parasitic resonance of lead or trace inductance working against the supply bypass capacitors. the opposite is true for ltc1645 hot swap circuits on a daughterboard. in most cases, on the powered side of the n-channel fet switches (v cc n ) there is no supply bypass capacitor present. an abrupt connection, produced by plugging a board into a backplane connector, results in a fast rising edge applied to the v cc n line of the ltc1645. applicatio s i for atio wu uu figure 4. supply turning off figure 3. supply turning on figure 2. typical hot swap connection r sense2 q1 q2 r2 10 c2 c timer c load1 c load2 r1 10 c1 12 1 2 3 8 9 6 5 11 7 13 14 10 4 v cc1 on fault sense1 gate2 v cc2 v cc2 v cc1 v out2 v out1 ltc1645 (14-lead) timer gnd comp + compout fb sense2 gate1 1645 f02 reset + + r sense1 v cc n v out n v cc n + ? v gate 1645 f03 t 1 t 2 gate n slope = 10 a/c n v cc n v out n v cc n + ? v gate 1645 f04 t 3 t 4 gate n slope = 40 a/c n
9 ltc1645 applicatio s i for atio wu uu (a) undamped v cc waveform (48" leads) (b) undamped v cc waveform (8" leads) figure 5. ring experiment no bulk capacitance is present to slow the rate of rise and heavily damp the parasitic resonance. instead, the fast edge shock excites a resonant circuit formed by a combi- nation of wiring harness, backplane and circuit board parasitic inductances and fet capacitance. in theory, the peak voltage should rise to 2x the input supply, but in practice the peak can reach 2.5x, owing to the effects of voltage dependent fet capacitance. the absolute maximum v cc n potential for the ltc1645 is 13.2v; any circuit with an input of 5v or greater should be scrutinized for ringing. a well-bypassed backplane should not escape suspicion: circuit board trace inductances of as little as 10nh can produce sufficient ringing to overvoltage v cc . check ringing with a fast storage oscilloscope (such as a lecroy 9314al dso) by attaching coax or a probe to v cc and gnd, then repeatedly inserting the circuit board into the backplane. figures 5a and 5b show typical results in a 12v application with different v cc lead lengths. the peak amplitude reaches 22v, breaking down the esd protection diode in the process. there are two methods for eliminating ringing: clipping and snubbing. a transient voltage suppressor is an effec- tive means of limiting peak voltage to a safe level. figure 6 shows the effect of adding an on semiconductor, 1sma12cat3, on the waveform of figure 5. figures 7a and 7b show the effects of snubbing with different rc networks. the capacitor value is chosen as 10x to 100x the fet c oss under bias and r is selected for best damping1 w to 50 w depending on the value of parasitic inductance. v out 0.1 f 1645 f05 10 r1 0.01 12v irf7413 c load + + ltc1645 power leads scope probe 8' 1 s/div 1645 f05a 4v/div 0v 24v 1 s/div 4v/div 1645 f05b 0v 24v
10 ltc1645 applicatio s i for atio wu uu v cc waveform clamped by a transient suppressor figure 6. transient suppressor clamp v out 0.1 f 1645 f06 10 d1* on semiconductor * 1sma12cat3 r1 0.01 12v irf7413 c load + + ltc1645 power leads backplane connector pcb edge connector 1 s/div 1645 f06a 2v/div 0v 12v (a) v cc waveform damped by a snubber (15 w , 6.8nf) (b) v cc waveform damped by a snubber (10 w , 0.1 m f) figure 7. snubber fixes v out 0.1 f 1645 f07 10 r1 0.01 12v irf7413 c load + + ltc1645 power leads backplane connector pcb edge connector 10 0.1 f 1 s/div 1645 f07a 2v/div 0v 12v 1 s/div 1645 f07b 2v/div 0v 12v
11 ltc1645 applicatio s i for atio wu uu (a) v cc short-circuit supply current glitch without any limiting (b) v cc supply glitch without any limiting (c) v cc short-circuit supply current glitch with 2 m h series inductor (d) v cc supply glitch with 2 m h series inductor figure 8. supply glitch supply glitching ltc1645 hot swap circuits on the backplane are generally used to provide power-up/down sequence at insertion/ removal as well as overload/short-circuit protection. if a short-circuit occurs at supply ramp-up, the circuit breaker trips. the partially enhanced fet is easily disconnected without any supply glitch. if a dead short occurs after a supply connection is made (figure 8), the sense resistor r1 and the r ds(on) of the fully enhanced fet provide a low impedance path for 0.1 f 1645 f08 10 r1 0.01 12v irf7413 2 h + ltc1645 supply glitch backplane connector board with possible short-circuit fault 100 f + 1 s/div 25a/div 1645 f08a 1 s/div 4v/div 1645 f08b v cc gate 1 s/div 5a/div 1645 f08c 1 s/div 4v/div 1645 f08d gate v cc
12 ltc1645 nearly unlimited current flow. the ltc1645 discharges the gate pin in a few microseconds, but during this discharge time current on the order of 150 amperes flows from the v cc power supply. this current spike glitches the power supply, causing v cc to dip (figure 8a and 8b). on recovery from overload, some supplies may over- shoot. other devices attached to this supply may reset or malfunction and the overshoot may also damage some components. an inductor (1 m h to 10 m h) in series with the fets source limits the short-circuit di/dt, thereby limiting the peak current and the supply glitch (figure 8c and 8d). additional power supply bypass capacitance also reduces the magnitude of the v cc glitch. reset the ltc1645 uses an internal 1.238v bandgap reference, a precision voltage comparator, and a resistive divider to monitor the output supply voltage (figure 9). whenever the voltage at the fb pin rises above its reset threshold (1.238v), the comparator output goes high, and a timing cycle starts (see figure 10, time points 1 and 4). after a complete timing cycle, reset is released. an external pull-up is required for the reset pin to rise to a logic high. when the voltage at the fb pin drops below its reset threshold, the comparator output goes low. after passing through a glitch filter, reset is pulled low (time point 2). if the fb pin rises above the reset threshold for less than a timing cycle, the reset output remains low (time point 3). applicatio s i for atio wu uu glitch filter the ltc1645 has a glitch filter to prevent reset from generating a spurious system reset in the presence of transients on the fb pin. the filter is 20 m s for large transients (greater than 150mv) and up to 80 m s for smaller transients. the relationship between glitch filter time and the transient voltage is shown in typical perfor- mance characteristics: glitch filter time vs feedback transient. timer the system timing for the ltc1645 is generated by the circuitry shown in figure 11. the timer is used to set the turn-on delay after the on pin goes high. it also sets the delay before the reset pin goes high after the fb pin exceeds 1.238v. whenever the timer is off, the internal n-channel shorts the timer pin to ground (figure 11). activating the timer connects a 2 m a current from v cc1 to the timer pin and the figure 10. supply monitor waveforms figure 9. supply monitor block diagram figure 11. system timing block diagram + comp timer c timer fb reset v out on timer p 10k 1645 f09 reset logic 1.238v reference v2 1 1.23v 1.23v 1645 f10 23 4 v1 v out timer reset v2 v1 v2 + comp timer 2 a c timer on 1.23v supply monitor 1645 f11 logic
13 ltc1645 voltage on the external capacitor c timer starts to ramp up with a slope dv/dt = 2 m a/c timer . when the voltage reaches the trip point (1.23v), the timer is reset by pulling the timer pin back to ground. the timer period is t = (1.23v ? c timer )/2 m a. for a 200ms delay, use a 0.33 m f capacitor. electronic circuit breaker the ltc1645 features an electronic circuit breaker func- tion that protects against short circuits or excessive out- put currents. by placing sense resistors between the supply inputs and sense pins of the supplies, the circuit breaker trips whenever the voltage across either sense resistor is greater than 50mv for more than 1.5 m s. if the circuit breaker trips, both gate pins are immediately pulled to ground and the external n-channels fets are quickly turned off (time point 6 in figure 12). the circuit breaker resets and another timing cycle starts by taking the on pin below 0.4v and then high as shown at time point 7. at the end of the timer cycle (time point 8), the charge pump turns on again. if the circuit breaker feature is not required, short the sense n pin to v cc n . if the 1.5 m s response time is too fast to reject supply noise, add external resistors and capacitors r f and c f to the sense circuit as shown in figure 13. the on pin the on pin is used to control system operation as shown in figure 14. at time point 1, the board makes connection and the supplies power up the chip. at time point 2, the on pin goes high and a timer cycle starts as long as both v cc pins are higher than the undervoltage lockout trip point (2.23v for v cc1 and 1.12v for v cc2 ) and an overcurrent fault is not detected. at the end of the timer cycle (time point 3), the charge pump is turned on and the gate n pin voltages start to ramp up with the output supply voltages, v out n , following one gate-to-source voltage drop lower. at time point 4, v out2 reaches its power-good trip level (this example assumes the fb pin resistive divider is connected to v out2 ) and a timing cycle starts. at the end of the timing cycle (time point 5), reset goes high and the power-up process is complete. applicatio s i for atio wu uu figure 13. extending the short-circuit protection delay figure 12. current fault timing figure 14. on pin waveforms 1645 f14 on 0.8v 0.4v 0v 2v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 gate1 gate2 v out1 v out2 timer v cc n reset ramping up and down together ramping up and turning off fast ramping up and down separately sense n ltc1645 gate n v cc n 1645 g13 c f r f reset v out n gate n 1645 f12 timer on v cc n ?v sense n v cc n 12 3 4 ramping up reset fault and ramp up current fault 56 7 89 10
14 ltc1645 an external hard reset is initiated at time point 6. the on pin is forced below 0.8v but above 0.4v, and the gate n pin voltages start to ramp down. v out n also starts to ramp down, and reset goes low when v out2 drops below the power-good trip level at time point 7. time points 8 to 15 are similar to time points 1 to 7, except the on pins different voltage thresholds are used to ramp v out1 and v out2 separately. at time point 8, the on pin goes above 0.8v but below 2v, and one timing cycle later (time point 9) gate1 begins to ramp up with v out1 following one gate-to-source voltage drop lower. at time point 10, the on pin goes above 2v and gate2 immedi- ately begins ramping up with v out2 following one gate-to- source voltage drop lower. as soon as v out2 reaches its power-good trip level at time point 11, a timing cycle starts. at the end of the timing cycle (time point 12), reset goes high and the power-up process is complete. the on pin is forced below 2v but above 0.8v at time point 13 and the gate2 pin voltage starts to ramp down. v out2 also starts to ramp down and reset goes low when v out2 drops below the power-good trip level at time point 14. when the on pin goes below 0.8v but above 0.4v at time point 15, gate1 and v out1 ramp down. time points 16 to 19 show the same power-up sequence as time points 2 to 5, while time point 20 demonstrates the gate n pins being pulled immediately to ground (instead of ramping down) by the on pin going below 0.4v. power supply tracking and sequencing applications the ltc1645 is able to sequence v out n in a number of ways, including ramping v out1 up first and down last; ramping v out1 up first and down first; ramping v out1 up first and v out1 and v out2 down together; and ramping v out1 and v out2 up and down together. figure 15 shows an application ramping v out1 and v out2 up and down together. the on pin must reach 0.8v to ramp up v out1 and v out2 . the spare comparator pulls the on pin low until v cc2 is above 2.3v, and the on pin cannot reach 0.8v before v cc1 is above 3v. thus, both input supplies must be within regulation before a timing cycle can start. at the end of the timing cycle, the output voltages ramp up together. if either input supply falls out of regulation, the gates of q1 and q2 are pulled low together. figure 16 shows an oscilloscope photo of the circuit in figure 15. applicatio s i for atio wu uu figure 15. ramping 3.3v and 2.5v up and down together q1 1/2 si4920dy q2 1/2 si4920dy 0.01 * 0.01 * 10 10 1.18k 1% 10k 1.37k 1% 0.1 f 25v 0.33 f *wsl1206-01-1% (vishay dale) c load1 c load2 d1 1n4002 d3 mbr0530t1 d2 1n4002 1 2 3 8 9 6 5 11 7 13 12 14 both current limits: 5a 10 4 v cc1 on fault timer gnd sense1 gate2 gate1 v cc2 trip point: 3v v in1 3.3v v in2 2.5v v out1 3.3v 2.5a v out2 2.5v 2.5a p reset ltc1645 (14-lead) comp + compout fb sense2 1645 f15 reset + + 1.18k 1% 4.99k 1% 10k 1.37k 1% 1.82k 1%
15 ltc1645 v in2 5v/div v in1 5v/div v out2 5v/div v out1 5v/div timer 2v/div reset 5v/div figure 16. ramping 3.3v and 2.5v up and down together applicatio s i for atio wu uu this circuit guarantees that: (1) v out1 never exceeds v out2 by more than 1.2v, and (2) v out2 is never greater than v out1 by more than 0.4v. on power-up, v out1 and v out2 ramp up together. on power-down, the ltc1645 turns off q1 and q2 simultaneously. charge remains stored on c load1 and c load2 and the output voltages will vary depending on the loads. d1 and d2 turn on at ? 1v ( ? 0.5v each), ensuring condition 1 is satisfied, while d3 prevents violations of condition 2. different diodes may be necessary for different output voltage configurations. barring an overvoltage condition at the input(s), the only time these diodes might conduct current is during a power-down event, and then only to discharge c load1 or c load2 . in the case of an input overvoltage condition that causes excess current to flow, the circuit breaker will trip if the current limit level is set appropriately. figure 17 shows an application circuit where v out1 ramps up before v out2 . v out1 is initially discharged and d1 is reverse-biased, thus the voltage at the on pin is determined only by v cc1 through the resistor divider r1 and r2. the voltage at the on pin exceeds 0.8v if v cc1 is above 4.6v and v out1 begins to ramp up after a timing cycle. as v out1 ramps up, d1 becomes forward-biased and pulls the on pin above 2v when v out1 ? 4.5v. this turns on gate2 and v out2 ramps up. the fb comparator monitors v out2 , and the spare comparator monitors v out1 with r hyst creating ? 50mv of hysteresis. power supply multiplexer using back-to-back fets, the ltc1645 can hot swap two supplies to the same output, automatically selecting the primary supply if present or the secondary supply if the primary supply is not available. referring to figure 18, a diode-or circuit provides power to the ltc1645 if either supply is up. schottky diodes are used to prevent the voltage at v cc1 from approaching the undervoltage lock- out threshold. this application assumes that if a supply is not present, the supply input is floating. if only the 3.3v supply is present, the voltage at the comp + pin is below the trip point and compout pulls the base of q3 low, allowing the gate1 pin to ramp up normally. the voltage at the on pin exceeds 0.8v if the 3.3v supply is greater than 3v, ramping up gate1 and turning on q1a and q1b. the on pin does not exceed 2v (unless the 3.3v supply exceeds 7.5v!), keeping gate2 low and q2a and q2b off. if only the 5v supply is present or if both supplies are present, the comp + pin is above 1.238v and compout allows the base of q3 to be pulled high by r2. this turns q3 on, keeping gate1 low and q1a and q1b off. the voltage at the on pin is pulled above 2v by r1 and gate2 turns q2a and q2b on.
16 ltc1645 figure 17. ramping up 5v followed by 3.3v irf7413 irf7413 10 10 28k 1% r hyst 681k 14.7k 1% 10k 1% 0.01 f 25v 0.33 f 1 12 2 3 8 9 6 5 11 7 10 4 on fault timer gnd 13 14 v cc1 sense1 gate2 gate1 v cc2 v in2 3.3v v in1 5v v out1 5v 5a d1 1n4148 v out2 3.3v 5a ltc1645 (14-lead) comp + compout fb sense2 fault 1645 f17 0.01 f 25v reset + c load1 c load2 + 10k r1 47.5k 1% r2 10k 1% 10k 10k 10k 1% p reset2 p reset 0.005 * 0.005 * 13k 1% *lrf1206-01-r005-j (irc) both current limits: 10a applicatio s i for atio wu uu figure 18. power supply multiplexer q1a q1b 10 r2 10k 0.1 f 25v 0.33 f 10 1 12 2 3 8 9 6 5 11 7 13 14 10 4 v cc1 on fault timer gnd sense1 gate2 gate1 v cc2 v in1 3.3v v in2 5v d1 1/2 bat54c d2 1/2 bat54c q3 pn2222 v out 5v or 3.3v 5a ltc1645 (14-lead) comp + compout fb sense2 1645 f18 0.1 f 25v reset 22.6k 1% r1 10k 10k 10k 11.3k 1% irf7313 q2a q2b irf7313
17 ltc1645 applicatio s i for atio wu uu using the ltc1645 as a linear regulator this application uses the ltc1645 to hot swap one primary supply and generate a secondary low dropout regulated supply. figure 19 shows how to switch a 5v supply and create a 3.3v supply using the spare compara- tor and one additional transistor. the comp + pin is used to monitor the 3.3v output. as the voltage on the gate of q2 increases, the 3.3v output increases. at the 3.3v threshold the spare comparator trips. the compout pin goes high which turns on q3. this lowers the voltage on the gate of q2. this feedback loop is compensated by capacitors c1 and c2 and resistor r1. when power is first applied, the fb pin is low and reset holds one side of c2 low, slowing the ramp-up of v out2 . as v out2 exceeds 2.75v, reset releases to allow improved loop transient response. figure 20 shows the load transient response and voltage ripple of the generated supply. q1 irf7413 0.01 * 0.01 * q2 irfz24 10 10k 10 r1 200k 1m q3 pn2222 1.5k 1% 12.1k 1% 10k 1% 2.49k 1% c2 0.1 f 25v c1 0.033 f 0.1 f 25v 0.33 f 470 f** 6v 2 c load1 12 1 2 3 8 9 6 both current limits: 5a 5 11 7 13 14 10 4 v cc1 on fault sense1 timer gnd gate2 v cc2 v in 5v v out2 3.3v 2.5a v out1 5v 2.5a ltc1645 (14-lead) comp + compout fb sense2 gate1 1645 f19 reset + + lrf1206-01-r010-j (irc) t510x477k006as (kemet) * ** figure 19. switching 5v and generating 3.3v v out2 0.1v/div i out2 1a/div 2.5a 0.5a figure 20. load transient response and voltage ripple
18 ltc1645 applicatio s i for atio wu uu switching regulator supply sequencing figure 21 shows the ltc1645 sequencing two power supplies, the lower of which is generated by the ltc1430a switching regulator. connecting the regulators fb pin resistor divider (r1 and r2) to the other side of the pass fet (q1) allows the ltc1430a to compensate for the voltage drop across r sense1 and q1, assuring an accurate voltage output. the spare comparator holds the ltc1645s on pin low until the ltc1430as output is at least 3v, and shuts both channels off if it drops below 3v. when the on/off signal is taken high to 5v (turn-on), the voltage at the on pin rises with an rc exponential characteristic, reaching 0.8v first. this starts a timing cycle, and gate1 begins to rise. gate2 starts to ramp up after the on pin reaches 2v. as long as the timing cycle is shorter than the time for the on pin to rise from 0.8v to 2v, v out2 ramps up after v out1 . reset goes high one timing cycle after v out1 exceeds 3v. when the on/off signal is brought low, the voltage at the on pin exponentially decays and gate2 ramps down before gate1. reset goes low as soon as v out1 falls below 3v. figure 22 shows the power- up and power-down sequences of the circuit in figure 21. switching regulator hot swapping high current switching regulators usually require large bypass capacitors on both input and output for proper operation. the application in figure 23 controls the inrush current to the ltc1649s input bypass capacitors and ramps the two output voltages up and down together. as with the previous application, connecting the regulators fb pin resistor divider to the other side of the output pass fet (q2) allows the ltc1649 to compensate for the voltage drop across q2, assuring an accurate voltage output. the voltage at the ltc1645s on pin reaches 0.8v when v in exceeds 3v, and gate1 begins to ramp up one timing cycle later. as the regulators output rises, d2 pulls the on pin above 2v and gate2 begins to rise, ramping v out1 and v out2 up together. reset goes high one timing cycle after v out1 exceeds 3v and v out2 exceeds 2.35v. figure 24 shows the circuit in figure 23 powering up. care should be taken connecting a switching regulators fb or sense pins to a node other than its output. depend- ing on the regulators internal architecture, unusual be- havior may occur as it tries in vain to raise the voltage at on 2v/div v out1 2v/div v regout 2v/div figure 22. switching regulator supply sequencing v out2 2v/div reset 5v/div
19 ltc1645 q2 1/2 si4920dy q1 1/2 si4920dy 10 10 2.67k 1% 3.16k 1% 1.87k 1% 0.047 f 25v 1 f v regout 1 f 4700pf 0.1 f 2.4 h cdrh1272r4 0.33 f 1 12 2 3 8 9 6 5 11 7 10 4 on fault timer gnd 13 14 sense1 v cc1 gate2 gate1 v cc2 v in 5v v out1 3.3v 2.5a v out2 5v 2.5a ltc1645 (14-lead) comp + compout fb sense2 on/off fault 1645 f21 0.047 f 25v reset + c load1 c load2 + 1500 f 6.3v 2 + 130k 1% 162k 1% 22k 10k 51 1 mbrs130t3 si4410dy si4410dy mbr0530t1 10k 1.15k 1% reset r sense2 * 0.01 r sense1 * 0.01 r1 16.5k 1% r2 16.9k 1% *lrf1206-01-r010-j (irc) 0.1 f 15 f 10v 1500 f 6.3v 3 1 f 4700pf 270pf 680pf 2 1 4 3 7 8 5 6 pv cc2 g2 shdn comp pv cc1 g1 fb gnd ltc1430acs8 + + figure 21. switching regulator supply sequencing applicatio s i for atio wu uu
20 ltc1645 figure 23. switching regulator hot swap q1 fdb8030l q2 fdb8030l q3 fds6680 10 1500 f 6.3v 6 1500 f 6.3v 4 10 220 mbr0530lt1 1.02k 1% 2.67k 1% 1.13k 1% 0.01 f 25v 1 f 220pf 0.015 f 0.01 f 1 f 1 f 2200pf 5.1 1.2 h ? v regout v regin ** 100 f 0.33 f 0.1 f 100k mbr0530lt1 0.1 f 0.1 f 0.33 f 0.01 f 1 12 2 3 8 9 6 5 11 7 10 4 on fault timer gnd 13 14 v cc1 sense1 gate2 gate1 v cc2 v out1 3.3v 10a ltc1645 (14-lead) comp + compout fb sense2 fault 1645 f23 0.047 f 25v 3.01k 1% 3.09k 1% reset + + c load2 + c load1 + v out2 2.5v 15a v in 3.3v gnd 10k 4.99k 1% 1.82k 1% d2 mbr0530t1 10k 33k r2 1k r1 1.8k d1 1n4148 1.87k 1% gnd reset 0.003 * 0.003 * *lrf2010-01-r003-j (irc) **mbrs340t (on semiconductor) ? etqp6f1r2hfa (panasonic) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 0.33 f 0.1 f 18k 1k irf7801 irf7801 irf7801 irf7801 g2 pv cc2 v cc i fb i max comp cpout c + g1 pv cc1 gnd fb shdn ss v in c ltc1649 10 f + + 10 applicatio s i for atio wu uu
21 ltc1645 table 1. n-channel selection guide current part level number manufacturer description 1a to 2a ndh8503n fairchild dual n-channel r ds(on) = 0.033 supersot-8 1a to 2a si6928dq siliconix dual n-channel r ds(on) = 0.035 tssop-8 2a to 5a si4920dy siliconix dual n-channel r ds(on) = 0.025 so-8 2a to 5a irf7313 international dual n-channel rectifier r ds(on) = 0.029 supersot-8 5a to 10a si4420 siliconix single n-channel r ds(on) = 0.009 so-8 5a to 10a fds6680 fairchild single n-channel r ds(on) = 0.01 so-8 5a to 10a irf7413 international single n-channel rectifier r ds(on) = 0.011 so-8 5a to 10a mmsf3300 on semiconductor single n-channel r ds(on) = 0.0125 so-8 10a to 20a fdb8030l fairchild single n-channel r ds(on) = 0.0035 to-263ab 10a to 20a sud75n03-04 siliconix single n-channel r ds(on) = 0.004 d 2 pak on 2v/div v out2 2v/div v regout 2v/div figure 24. switching regulator hot swap v out1 2v/div v regin 2v/div reset 5v/div applicatio s i for atio wu uu v cc v out *user selected voltage clamp 1n4688 (5v) 1n4692 (7v): logic-level mosfet 1n4695 (9v) 1n4702 (15v): standard-level mosfet 1645 f25 r1 d1* d2 1n4148 d4* d2 1n4148 q1 figure 25. optional gate clamp its fb or sense pin. in the case of the ltc1649, large peak currents result if the fb pin is at ground and not connected directly to the output inductor and capacitors. to keep the peak currents under control, r1, r2 and d1 hold the fb pin above ground but below its normal regulated value until v out2 ramps up and d1 reverse-biases. power n-channel selection the r ds(on) of the external pass transistors must be low enough so that the voltage drop across them is 100mv or less at full current. if the r ds(on) is too high, the voltage drop across the transistor can cause the output voltage to trip the reset circuit. the transistors listed in table 1 or other similar transistors are recommended for use with the ltc1645. low voltage applications may require the use of logic-level fets; ensure their maximum v gs rating is sufficient for the application. gate voltage as a function of v cc is illustrated in the typical performance curves. if lower gate drive is desired, connect a diode in series with a zener between gate and v cc or between gate and v out as shown in figure 25.
22 ltc1645 s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** dimensions in inches (millimeters) unless otherwise noted. u package descriptio
23 ltc1645 dimensions in inches (millimeters) unless otherwise noted. s package 14-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 14 13 0.337 ?0.344* (8.560 ?8.738) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 5 6 7 8 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) s14 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc1645 1645f lt/tp 0400 4k ? printed in usa ? linear technology corporation 1999 related parts part number description comments ltc1421 hot swap controller dual supplies from 3v to 12v, additionally C 12v ltc1422 hot swap controller single supply hot swap in so-8 from 3v to 12v lt1640l/lt1640h negative voltage hot swap controllers negative high voltage supplies from C10v to C 80v lt1641 positive voltage hot swap controller positive high voltage supplies from 9v to 80v ltc1642 fault protected hot swap controller 3v to 15v, overvoltage protection up to 33v ltc1643l/ltc1643l-1/ pci-bus hot swap controllers 3.3v, 5v, 12v, C12v supplies for pci bus ltc1643h ltc1647 dual hot swap controller dual on pins for supplies from 3v to 15v linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com q1 1/2 si4920dy q2 1/2 si4920dy 0.01 * 0.01 * 10 10 1.18k 1% 10k 1.37k 1% 0.1 f 25v 0.33 f *wsl1206-01-1% (vishay dale) c load1 c load2 d1 1n4002 d3 mbr0530t1 d2 1n4002 1 2 3 8 9 6 5 11 7 13 12 14 both current limits: 5a 10 4 v cc1 on fault timer gnd sense1 gate2 gate1 v cc2 trip point: 3v v in1 3.3v v in2 2.5v v out1 3.3v 2.5a v out2 2.5v 2.5a p reset ltc1645 (14-lead) comp + compout fb sense2 1645 f15 reset + + 1.18k 1% 4.99k 1% 10k 1.37k 1% 1.82k 1% dual supply hot swap with tracking outputs typical applicatio u

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